ComScire True Random Number Generator Technology and Patents
Development of the technology underlying ComScire’s true random number generators began around January, 1994 when inventor and entrepreneur Scott A. Wilber designed and built his first prototype hardware random generator. The generator, shown here, used a thermal noise source and provided random signals to a computer through an analog-to-digital converter. Mr. Wilber subsequently developed his generators into a mass-producible form with an easy to use parallel port interface.
The Model J20KP was offered for sale shortly after the first patent was filed in February, 1995. The J20KP was powered by tiny currents available through the parallel port connections and provided 20 thousand high quality true random bits per second for easy use on personal computers. This first-of-its-kind generator marked the beginning of a new era of data security. Now virtually every computer includes some form of true random number generator providing secure keys and other essential functionality.
ComScire has developed and sold four generations of hardware models with increasing capabilities, as well as a separately patented software-enabled TRNG for use on PC’s. Every hardware model has proven to be extremely reliable with only one confirmed component failure in over 20 years. This is estimated to represent over 10 million cumulative hours of operation.
We supply hardware generators of the highest quality, reliability and ease of use available anywhere. Current models include continuous testing of every raw generated bit and every output bit, and a failsafe shutdown if any fault is detected. The output sequences of ComScire’s hardware generators are guaranteed to pass any correctly designed test for randomness, which is the highest standard in the world.
Visit the Generator Selection Guide page to compare and determine which ComScire True Random Number Generator is right for your application.
ComScire PureQuantum® random number generators – unprecedented security for the information age.
Entropy Analysis and System Design for Quantum Random Number Generators in CMOS Integrated Circuits
A quantum random number generator is implemented in an integrated circuit without the need for complex, bulky and expensive measurement equipment and circuitry. Quantum entropy, chaotic entropy and pseudo-entropy are defined and their combinations mathematically described. Models and design equations are provided for estimating the quantum entropy in the form of shot noise due to sub-threshold leakage, gate tunneling leakage and junction tunneling leakage in MOS transistors and CMOS IC’s.
Entropy Analysis and System Design for Quantum Random Number Generators in CMOS Integrated Circuits [HTML]
Entropy, Predictability and Post-Quantum RNG Design
The emergence of quantum computers and potential quantum eavesdropping may make many of the current methods of encryption and information security obsolete within a very few years [MOS15, NI16a]. A clear understanding of the fundamentals of randomness and random number generators is required to address the ever-changing needs of security designers. The proper use of entropy can make certain “chaotic” generators as unpredictable as any quantum RNG, while typically used deterministic post processing methods can result in an overestimation of nondeterminism. Post-quantum randomness may also need to take into account quantum nonlocality, which puts special new requirements on the design of random number generators.
Designing Nondeterministic Random Number Generators [HTML]
Patents and Applications
US Patent Number 6,862,605
True random number generator and entropy calculation device and method.
A random number generator includes a first oscillator that provides a first oscillatory signal to a processor, and a second oscillator that provides a signal to a frequency multiplier, which in turn provides a second oscillatory signal to the processor. The relative jitter between the two oscillatory signals contains a calculable amount of entropy that is extracted by the processor to produce a sequence of true random numbers.
US Patent Number 6,862,605 [HTML]
US Patent Numbers 6,324,558, 6,763,364, 7,096,242 and 7,752,247
Random number generator and generation method
An RNG circuit is connected to the parallel port of a computer. The circuit includes a flat source of white noise and a CMOS amplifier circuit compensated in the high frequency range. A low-frequency cut-off is selected to maintain high band-width yet eliminate the 1/f amplifier noise tail. A CMOS comparator with a 10 nanosecond rise time converts the analog signal to a binary one. A shift register converts the serial signal to a 4-bit parallel one at a sample rate selected at the knee of the serial dependence curve. Two levels of XOR defect correction produce a BRS at 20 kHz, which is converted to a 4-bit parallel word, latched and buffered. The entire circuit is powered from the data pins of the parallel port. A device driver interface in the computer operates the RNG. The randomness defects with various levels of correction and sample rates are calculated and the RNG is optimized before manufacture.
US Patent Number 6,324,558 [HTML]
US Patent Number 6,763,364
US Patent Number 7,096,242
US Patent Number 7,752,247
Reexamination Certificate for 6,763,364
Reexamination Certificate for 7,096,242